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1 low power mono audio codec features system ? high performance and low power multi - bit delta - sigma audio adc and dac ? i 2 s/pcm master or slave serial da ta port ? two pairs of analog input with differential input option ? mono analog output ? 256 /384fs , u sb 12/ 24 mhz , f ractional pll for wide range of system clocks ? standard audio clock output ? sophisticated analog input and output routing, mixing and gain ? gpio ? i 2 c interface adc ? 24- bit, 8 to 96 khz sampling frequency ? 9 5 db signal to noise ratio, - 85 db thd+n ? low noise pre - amplifier ? noise reduction filters ? auto level control (alc) and noise gate ? support analog and digital microphone ? microphone bias dac ? 24- bit, 8 to 96 khz sampling frequency ? 9 5 db signal to noise ratio, - 85 db thd+n ? 1.25w@8 ?/5v or 1.8w@4?/4.2v mono class d speaker driver ? dynamic range compression ? headphone and external mic detection ? pop and click noise suppression low power ? 3.3v to 5 v operation ? 32 mw playback; 4 2 mw playback and record ? low standby current applications ? car dv ? ip camera ? dvr, nvr ? surveillance o rdering i nformation es83 74 -40 c ~ +85 c qfn -28 ES8374
everest semiconductor confidential ES8374 revision 9 2 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 1. block diagram dvdd pvdd dgnd avdd agnd spkvdd spkgnd adcvref dacvref vmid micbias mclk cdata cclk ce gpio1 gpio2 dsdin asdout sclk dlrck lin2 lin1 rin1 rin2 i 2 c gpio mic bias mixer hp driver pga power supply i 2 s/pcm adc alc dac drc noise filter mono dac monoout mono adc analog reference pga lin2 lin1 clock mgr/pll class d driver spkp spkn
everest semiconductor confidential ES8374 revision 9 3 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com ES8374 spkp spkvdd spkgnd spkn dsdin lrck asdout 14 13 12 11 10 9 8 rin2 lin2 rin1 lin1/dmic_sda gpio1 ce cdata 22 23 24 25 26 27 28 2. pin out and description name i/o description mclk di master clock cdata dio i 2 c data cclk di i 2 c clock ce di i 2 c address gpio1 dio gpio (digital mic clock, jack detect, pll out, interrupt) gpio2 dio gpio (pll out, interrupt) asdout d o i 2 s/pcm serial data out dsdin di i 2 s/pcm serial data in lrck dio i 2 s/pcm left and right clock sclk dio i 2 s/pcm bit clock lin1/dmic_sda ai left analog input or digital mic data rin1 ai right analog input lin2 ai left analog input rin2 ai right analog input monoout ao mono output spkp ao positive speaker out spkn ao negative speaker out micbias mic bias adcvrp adc reference filtering dacvrp dac reference filtering vmid common mode filtering dvdd digital core power supply pvdd digital io power supply dgnd digital ground avdd analog power supply agnd analog ground spkvdd speaker driver power supply spkgnd speaker driver ground cclk mclk dgnd gpio2 pvdd dvdd sclk 1 2 3 4 5 6 7 micbias vmid adcvref dacvref agnd avdd monoout 21 20 19 18 17 16 15
everest semiconductor confidential ES8374 revision 9 4 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 3. typical application circuit 4. clock modes and samp ling frequencies the device supports three types of clocking: standard audio clocks (256fs, 384fs, 512fs, etc), usb clocks (12/24 mhz), and an on - chip 22 - bit fractional pll clock. according to the serial audio data sampling frequency (fs) , the device can work in two speed modes : single speed mode or double speed mode. in sing le speed mode, fs normally ranges from 8 khz to 48 khz, and in double speed mode, fs normally range from 64 khz to 96 khz. the device can work either in master clock mode or slave clock mode. in slave mode, lrck an d sclk are supplied externally, and lrck a nd sclk must be synchronously derived from the sy stem clock with specific rates. in master mode, lrck and sclk ar e derived internally from device master clock. 5. micro - controller configura tion interface the device supports standard i 2 c micro - controller configuration interface. external micro - controller can completely configure the device through writing to in ternal configuration registers. i 2 c interface is a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 1 . data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred mout _out avdd mi cb ias dvdd p vd d 0.1uf 0.1uf 1uf 1uf 1uf 1uf agnd 1uf vb a t 1uf cd ata 28 cc lk 1 m c lk 2 pllout /gpio2 4 p vd d 5 bc lk 7 asdout 8 dlrc k 9 adsin 10 spkvdd 13 spkgnd 12 spkln 11 agnd 17 dacvref 18 adcvref 19 vm id 20 mi cb ias 21 rin2 22 lin2 23 rin1 24 lin1/dmic-sda 25 dmiclk/gpio1 26 ce 27 dgnd 3 spklp 14 monoo ut 15 avdd 16 dvdd 6 pgnd 29 ever es t ES8374 agnd cpu/dsp agnd agnd agnd agnd agnd agnd agnd 1uf 1uf spe a ker 1uf dclk dout dmic agnd 0r in the layout, chip is treated as an analog device gnd(sys) agnd * * * * * * mi cb ias mic2p mic2n for the best performance,decoupling and filtering capacitors should be located as close to the device package as poss ible additional parallel capacitors(typically 0.1 f) can be used, larger value capacitors(typically 10 f) would also help * * *
everest semiconductor confidential ES8374 revision 9 5 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 4 00 k bps. figure 1 data transfer for i 2 c interface a master controller initiates the transmission by sending a start signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 0010 00x, where x equals ad0 . the rw bit indicates the slave data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the communication by ge nerating a stop signal, which is defined as a low -to - high transition at sda while scl is high. in i 2 c interface mode, the registers can be written and read. the formats of write and read instructions are shown in table 1 and table 2 . please note that , to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the re gister. table 1 write data to register in i 2 c interface mode chip address r/w register address data to be written 001000 ad0 0 ack ram ack data table 2 read data from register in i 2 c interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data 6. digital audio interf ace the device provides many formats of serial audio data interface to the input of the dac or out put from the adc through lrck, b c lk (sclk) and dacdat/adcdat pins. these formats are i 2 s, left justified, right justified, dsp/pcm and tdm mode. dac input dacdat is sampled by the
everest semiconductor confidential ES8374 revision 9 6 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com device on the rising edge of sclk. adc data is out at adcdat on the falling edge of sclk. the relationship of sdata (dacdat/adcdat ), sclk and lrck with these formats are shown through figure 2 to figure 6 . n-2 n-1 n 3 2 1 1 sclk msb lsb left channel n-2 n-1 n 3 2 1 1 sclk msb lsb right channel sdata sclk lrck figure 2 i 2 s serial audio da ta format up to 24 - bit n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 3 left justified serial audio data format up to 24 - bit figure 4 dsp/pcm mode a figure 5 dsp/pcm mode b
everest semiconductor confidential ES8374 revision 9 7 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 7. electrical character istics absolute maximum rat ings continuous operation at or beyond these conditions may permanently damage the device. parameter min max analog supply voltage level - 0.3v + 5 . 5 v digital supply voltage level - 0.3v +5.5 v input voltage r ange dgnd - 0.3v p vdd+0.3v operating temperature range - 40 c +85 c storage temperature -65 c +150 c recommended operatin g conditions parameter min typ max unit avdd 3 3.3 5. 5 v spkvdd 4 ? speaker 8 ? speaker 3 3 4.2 5 5 5.5 v dvdd 3 3.3 5. 5 v pvdd (dvdd - input high level < 2v) 1. 6 3.3 5. 5 v adc analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd= 3.3v, d vdd= 3.3 v, agnd=0v , dgnd=0v, ambient temperature= 25 c, fs=48 khz or 96 khz , mclk/lrck=256. parameter min typ max unit adc performance signal to noise ratio (a - weigh) 85 95 98 db thd+n - 88 - 85 - 75 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 50 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level vrms input impedance k
everest semiconductor confidential ES8374 revision 9 8 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com dac analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd=3.3v, dvdd=3.3 v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz or 96 khz , mclk/lrck=256. parameter min typ max unit dac performance signal to noise ratio (a - weigh) 83 9 5 98 db thd+n - 8 8 - 8 5 - 75 db filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 40 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 40 db analog output full scale output level vrms power consumption ch aracteristics parameter min typ max unit normal operation mode dvdd=3.3v, pvdd=3.3v, avdd=3.3v: play back play back and record 32 42 mw power down mode dvdd=3.3v, pvdd=3.3v, avdd=3.3v 50 ua serial audio port sw itching specificatio ns parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low tsclkl 15 ns sclk pulse width high tsclkh 15 ns sclk falling to lrck edge tslr C 10 10 ns sclk falling to sdout valid tsdo 0 ns sdin valid to sclk rising setup time tsdis 10 ns sclk rising to sdin hold time tsdih 10 ns
everest semiconductor confidential ES8374 revision 9 9 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 6 serial audio port timing i 2 c switching specificat ions parameter symbol min max unit scl clock frequency f scl 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us sda hold time from scl falling t twdh 900 ns sda setup time to scl rising t twds 100 ns rise time of scl t twr 300 ns fall time scl t twf 300 ns s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 7 i 2 c timing
everest semiconductor confidential ES8374 revision 9 10 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 8. package
everest semiconductor confidential ES8374 revision 9 11 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 9. corpo rate information everest semiconductor co., ltd. ????? 1355 ???? , ? 215021 email: info@everest - semi.com

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